CARME-M4 BSP  V1.5
+ Collaboration diagram for FSMC_NOR_SRAM_Controller:

Modules

 FSMC_Data_Address_Bus_Multiplexing
 
 FSMC_Memory_Type
 
 FSMC_Data_Width
 
 FSMC_Burst_Access_Mode
 
 FSMC_AsynchronousWait
 
 FSMC_Wait_Signal_Polarity
 
 FSMC_Wrap_Mode
 
 FSMC_Wait_Timing
 
 FSMC_Write_Operation
 
 FSMC_Wait_Signal
 
 FSMC_Extended_Mode
 
 FSMC_Write_Burst
 
 FSMC_Address_Setup_Time
 
 FSMC_Address_Hold_Time
 
 FSMC_Data_Setup_Time
 
 FSMC_Bus_Turn_around_Duration
 
 FSMC_CLK_Division
 
 FSMC_Data_Latency
 
 FSMC_Access_Mode
 

Detailed Description