CARME-M4 BSP  V1.5
gpio_asm.s

This example shows how to create an output gpio pin in assembler.

/*
* This example shows how to create an output gpio pin in assembler.
*/
.syntax unified
.cpu cortex-m4
.thumb
.global main
main:
/*
* RCC
*/
LDR r1, =0x40023800 // RCC_BASE
/* enable RCC for GPIOA */
LDR r3, [r1, #0x30] // RCC->AHB1ENR
LDR r2, =0x1 // RCC_AHB1Periph_GPIOA
ORR r3, r3, r2 // RCC->AHB1ENR |= RCC_AHB1Periph_GPIOA
STR r3, [r1, #0x30]
/*
* GPIOA
*/
LDR r1, =0x40020000 // GPIOA_BASE
/*
* Port: GPIOA
* Pin: GPIO_Pin_0
* Mode: Output
* Speed: 100MHz
* PuPd: No PU/PD
*/
/* GPIO port mode register */
LDR r3, [r1, #0x00] // GPIOA->MODER
LDR r2, =0x00000003
BIC r3, r3, r2 // GPIOA->MODER &= ~(GPIO_MODER_MODER0 << (GPIO_PinSource0 * 2));
LDR r2, =0x00000001
ORR r3, r3, r2 // GPIOA->MODER |= (GPIO_MODER_MODER0_0 << (GPIO_PinSource0 * 2));
STR r3, [r1, #0x00]
/* GPIO port output type register */
LDR r3, [r1, #0x04] // GPIOA->OTYPER
LDR r2, =0x00000001
BIC r3, r3, r2 // GPIOA->OTYPER &= !(1 << GPIO_PinSource0);
STR r3, [r1, #0x04]
/* GPIO port output speed register */
LDR r3, [r1, #0x08] // GPIOA->OSPEEDR
LDR r2, =0x00000003
ORR r3, r3, r2 // GPIOA->OSPEEDR |= (0x03 << (GPIO_PinSource0 * 2));
STR r3, [r1, #0x08]
/* GPIO port pull-up/pull-down register */
LDR r3, [r1, #0x0C] // GPIOA->PUPDR
LDR r2, =0x00000003
BIC r3, r3, r2 // GPIOA->PUPDR &= ~(0x03 << (GPIO_PinSource0 * 2));
STR r3, [r1, #0x0C]
/* GPIO port bit set/reset register */
LDR r4, =0x00000001 // Bit_SET
LDR r5, =0x00010000 // Bit_RESET
loop:
STR r4, [r1, #0x18] // GPIOA->BSRR |= GPIO_Pin_0
STR r5, [r1, #0x18] // GPIOA->BSRR |= (GPIO_Pin_0 << 16)
B loop