CARME-M4 BSP  V1.5
can_sja1000.h
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1 #ifndef __CAN_SJA1000_H__
2 #define __CAN_SJA1000_H__
3 
74 #ifdef __cplusplus
75 extern "C" {
76 #endif /* __cplusplus */
77 
78 /*----- Header-Files -------------------------------------------------------*/
79 #include <carme.h> /* CARME Module */
80 
81 /*----- Macros -------------------------------------------------------------*/
82 /*****************************************************************************
83  * REGISTERS (PeliCAN Mode)
84  ****************************************************************************/
85 #define SJA1000_MOD 0x00
86 #define SJA1000_CMR 0x01
87 #define SJA1000_SR 0x02
88 #define SJA1000_IR 0x03
89 #define SJA1000_IER 0x04
90 /* reserved 0x05 */
91 #define SJA1000_BTR0 0x06
92 #define SJA1000_BTR1 0x07
93 #define SJA1000_OCR 0x08
94 /* test 0x09 */
95 /* reserved 0x0a */
96 #define SJA1000_ALC 0x0b
97 #define SJA1000_ECC 0x0c
98 #define SJA1000_EWL 0x0d
99 #define SJA1000_RXERR 0x0e
100 #define SJA1000_TXERR 0x0f
101 #define SJA1000_RMC 0x1d
102 #define SJA1000_RBSA 0x1e
103 #define SJA1000_CDR 0x1f
104 #define SJA1000_ACR(_n_) (0x10 +_n_)
105 #define SJA1000_AMR(_n_) (0x14 +_n_)
106 #define SJA1000_RX_BUF(_n_) (0x10 +_n_)
107 #define SJA1000_TX_BUF(_n_) (0x10 +_n_)
109 /*****************************************************************************
110  * FLAGS (PeliCAN Mode)
111  ****************************************************************************/
112 /* mode register */
113 #define SJA1000_MOD_SM (1<<4)
114 #define SJA1000_MOD_AFM (1<<3)
115 #define SJA1000_MOD_STM (1<<2)
116 #define SJA1000_MOD_LOM (1<<1)
117 #define SJA1000_MOD_RM (1<<0)
118 /* command register */
119 #define SJA1000_CMR_SRR (1<<4)
120 #define SJA1000_CMR_CDO (1<<3)
121 #define SJA1000_CMR_RRB (1<<2)
122 #define SJA1000_CMR_AT (1<<1)
123 #define SJA1000_CMR_TR (1<<0)
124 /* interrupt register */
125 #define SJA1000_IR_BEI (1<<7)
126 #define SJA1000_IR_ALI (1<<6)
127 #define SJA1000_IR_EPI (1<<5)
128 /* additional declarations are below */
129 
130 /* interrupt enable register */
131 #define SJA1000_IER_BEIE (1<<7)
132 #define SJA1000_IER_ALIE (1<<6)
133 #define SJA1000_IER_EPIE (1<<5)
134 #define SJA1000_IER_WUIE (1<<4)
135 #define SJA1000_IER_DOIE (1<<3)
136 #define SJA1000_IER_EIE (1<<2)
137 #define SJA1000_IER_TIE (1<<1)
138 #define SJA1000_IER_RIE (1<<0)
139 /* Frame information */
140 #define SJA1000_FRAMEINFO_FF (1<<7)
141 #define SJA1000_FRAMEINFO_RTR (1<<6)
142 /* status register */
143 #define SJA1000_SR_BS (1<<7)
144 #define SJA1000_SR_ES (1<<6)
145 #define SJA1000_SR_TS (1<<5)
146 #define SJA1000_SR_RS (1<<4)
147 #define SJA1000_SR_TCS (1<<3)
148 #define SJA1000_SR_TBS (1<<2)
149 #define SJA1000_SR_DOS (1<<1)
150 #define SJA1000_SR_RBS (1<<0)
151 /* interrupt register */
152 #define SJA1000_IR_WUI (1<<4)
153 #define SJA1000_IR_DOI (1<<3)
154 #define SJA1000_IR_EI (1<<2)
155 #define SJA1000_IR_TI (1<<1)
156 #define SJA1000_IR_RI (1<<0)
157 /* clock divider register (CDR) */
158 #define SJA1000_CDR_CANMODE (1<<7)
159 #define SJA1000_CDR_CBP (1<<6)
160 #define SJA1000_CDR_RXINTEN (1<<5)
161 #define SJA1000_CDR_CLOCK_OFF (1<<3)
163 /*----- Data types ---------------------------------------------------------*/
164 
165 /*----- Function prototypes ------------------------------------------------*/
166 
167 /*----- Data ---------------------------------------------------------------*/
168 
169 #ifdef __cplusplus
170 }
171 #endif /* __cplusplus */
172 
179 #endif /* __CAN_SJA1000_H__ */