CARME-M4 BSP  V1.5
Macros
RCC_PLL_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+ Collaboration diagram for RCC_PLL_Clock_Source:

Macros

#define RCC_PLLSource_HSI   ((uint32_t)0x00000000)
 
#define RCC_PLLSource_HSE   ((uint32_t)0x00400000)
 
#define IS_RCC_PLL_SOURCE(SOURCE)
 
#define IS_RCC_PLLM_VALUE(VALUE)   ((VALUE) <= 63)
 
#define IS_RCC_PLLN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
#define IS_RCC_PLLP_VALUE(VALUE)   (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
 
#define IS_RCC_PLLQ_VALUE(VALUE)   ((4 <= (VALUE)) && ((VALUE) <= 15))
 
#define IS_RCC_PLLI2SN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
#define IS_RCC_PLLI2SR_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 7))
 
#define IS_RCC_PLLI2SQ_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 15))
 
#define IS_RCC_PLLSAIN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
#define IS_RCC_PLLSAIQ_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 15))
 
#define IS_RCC_PLLSAIR_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 7))
 
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE)   ((1 <= (VALUE)) && ((VALUE) <= 32))
 
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE)   ((1 <= (VALUE)) && ((VALUE) <= 32))
 
#define RCC_PLLSAIDivR_Div2   ((uint32_t)0x00000000)
 
#define RCC_PLLSAIDivR_Div4   ((uint32_t)0x00010000)
 
#define RCC_PLLSAIDivR_Div8   ((uint32_t)0x00020000)
 
#define RCC_PLLSAIDivR_Div16   ((uint32_t)0x00030000)
 
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE)
 

Detailed Description

Macro Definition Documentation

#define IS_RCC_PLL_SOURCE (   SOURCE)
Value:
(((SOURCE) == RCC_PLLSource_HSI) || \
((SOURCE) == RCC_PLLSource_HSE))

Definition at line 79 of file stm32f4xx_rcc.h.

#define IS_RCC_PLLSAI_DIVR_VALUE (   VALUE)
Value:
(((VALUE) == RCC_PLLSAIDivR_Div2) ||\
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
((VALUE) == RCC_PLLSAIDivR_Div16))

Definition at line 101 of file stm32f4xx_rcc.h.