cs42l51.c

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#ifdef __cplusplus
 extern "C" {
#endif /* __cplusplus */

/*----- Header-Files -------------------------------------------------------*/
#include <stm32f4xx.h>              /* Processor STM32F407IG                */
#include <i2c.h>                    /* CARME I2C definitions                */
#include <i2s.h>                    /* CARME I2S definitions                */
#include <cs42l51.h>                /* cs42l51 audio codec definitions      */

/*----- Macros -------------------------------------------------------------*/

/*----- Data types ---------------------------------------------------------*/

/*----- Function prototypes ------------------------------------------------*/
void CS42L51_CtrlInterface_Init(void);
void CS42L51_AudioInterface_Init(void);

/*----- Data ---------------------------------------------------------------*/

/*----- Implementation -----------------------------------------------------*/
void CS42L51_WriteReg(uint8_t reg, uint8_t data) {

    CARME_I2C_Write(CODEC_I2C, CODEC_ADDRESS, (uint8_t) reg, 0, &data, 1);
}

uint8_t CS42L51_ReadReg(uint8_t reg) {

    uint8_t data;

    CARME_I2C_Read(CODEC_I2C, CODEC_ADDRESS, (uint8_t) reg, 0, &data, 1);
    return data;
}

uint8_t CS42L51_Init(int8_t Volume) {

    CS42L51_CtrlInterface_Init();
    CS42L51_AudioInterface_Init();

    /* Check if the codec is connected */
    if (CS42L51_ReadReg(CHIP_ID) != 0xD9) {
        return 1;
    }

    /* Keep Codec powered OFF */
    CS42L51_WriteReg(POWER_CONTROL, 0x01);

    CS42L51_WriteReg(MIC_POWER_AND_SPEED, 0x20);

    CS42L51_WriteReg(INTERFACE_CONTROL, 0x0C);

    CS42L51_WriteReg(MIC_CONTROL, 0x60);

    CS42L51_WriteReg(ADC_CONTROL, 0xA0);

    CS42L51_WriteReg(ADC_CONFIGURE, 0x00);

    CS42L51_WriteReg(DAC_OUTPUT_CONTROL, 0x60);

    CS42L51_WriteReg(DAC_CONTROL, 0x42);

    /* Set ALCAx and PGAx control */
    CS42L51_WriteReg(ALCA_AND_PGAA_CONTROL, 0x00);
    CS42L51_WriteReg(ALCB_AND_PGAB_CONTROL, 0x00);

    CS42L51_WriteReg(PCMA_MIXER_VOLUME_CONTROL, 0x00);
    CS42L51_WriteReg(PCMB_MIXER_VOLUME_CONTROL, 0x00);

    /* Set treble and bass */
    CS42L51_WriteReg(TONE_CONTROL, 0x88);

    /* Set the output volume */
    CS42L51_WriteReg(AOUTA_VOLUME_CONTROL, 0x18);
    CS42L51_WriteReg(AOUTB_VOLUME_CONTROL, 0x18);

    CS42L51_WriteReg(PCM_CHANNEL_MIXER, 0x00);

    CS42L51_WriteReg(LIMITER_THRESHOLD, 0x00);

    CS42L51_WriteReg(LIMITER_RELEASE, 0x7F);

    CS42L51_WriteReg(LIMITER_ATTACK, 0x00);

    /* Power down up after initial configure */
    CS42L51_WriteReg(POWER_CONTROL, 0x00);

//  CS42L51_WriteReg(BEEP_FREQUENCY_AND_TIMING, 0x0F);
//  CS42L51_WriteReg(BEEP_OFF_TIME_AND_VOLUME, 0x66);
//  CS42L51_WriteReg(BEEP_AND_TONE_CONFIGURATION, 0xC0);
    CS42L51_VolumeOutCtrl(Volume);

    return 0;
}

void CS42L51_CtrlInterface_Init(void) {

    CARME_I2C_Init(CODEC_I2C);
}

void CS42L51_AudioInterface_Init(void) {

    I2S_InitTypeDef I2S_InitStruct;

    /* Enable the peripheral clock */
    RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE);

    /* GPIO configuration */
    CARME_I2S_GPIO_Init();

    /* Deinitialize and disable the I2S and SPI hardware */
    SPI_Cmd(CODEC_I2S, DISABLE);
    I2S_Cmd(CODEC_I2S, DISABLE);
    I2S_Cmd(CODEC_I2S_EXT, DISABLE);
    SPI_I2S_DeInit(CODEC_I2S);

    /* CODEC_I2S peripheral configuration */
    I2S_InitStruct.I2S_AudioFreq = I2S_AudioFreq_48k;
    I2S_InitStruct.I2S_Standard = I2S_Standard_Phillips;
    I2S_InitStruct.I2S_DataFormat = I2S_DataFormat_16b;
    I2S_InitStruct.I2S_CPOL = I2S_CPOL_Low;
    I2S_InitStruct.I2S_Mode = I2S_Mode_MasterTx;
    I2S_InitStruct.I2S_MCLKOutput = I2S_MCLKOutput_Enable;

    /* Configure the I2S */
    I2S_Init(CODEC_I2S, &I2S_InitStruct);
    /* Initialize the I2S extended channel for RX */
    I2S_FullDuplexConfig(CODEC_I2S_EXT, &I2S_InitStruct);

    I2S_Cmd(CODEC_I2S, ENABLE);
    I2S_Cmd(CODEC_I2S_EXT, ENABLE);
}

uint8_t CS42L51_Status(void) {

    return CS42L51_ReadReg(STATUS_REGISTER);
}

void CS42L51_VolumeOutCtrl(int8_t Volume) {

//  uint8_t reg;
//
//  Volume &= 0x07;
//  Volume <<= 5;
//  reg = CS42L51_ReadReg(DAC_OUTPUT_CONTROL);
//  reg &= 0x1F;
//  reg |= Volume;
//
//  CS42L51_WriteReg(DAC_OUTPUT_CONTROL, reg);
    if (Volume > 0xE6) {
        /* Set the Master volume */
        CS42L51_WriteReg(AOUTA_VOLUME_CONTROL, Volume - 0xE7);
        CS42L51_WriteReg(AOUTB_VOLUME_CONTROL, Volume - 0xE7);
    }
    else {
        /* Set the Master volume */
        CS42L51_WriteReg(AOUTA_VOLUME_CONTROL, Volume + 0x19);
        CS42L51_WriteReg(AOUTB_VOLUME_CONTROL, Volume + 0x19);
    }
}

void CS42L51_Mute(uint8_t on) {

    uint8_t reg;

    reg = CS42L51_ReadReg(DAC_OUTPUT_CONTROL);

    if (on) {
        reg |= 0x03;
    }
    else {
        reg &= ~0x03;
    }

    CS42L51_WriteReg(DAC_OUTPUT_CONTROL, reg);
}

#ifdef __cplusplus
 }
#endif /* __cplusplus */