CARME-M4 BSP  V1.5
stm32f4xx_tim.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F4xx_TIM_H
31 #define __STM32F4xx_TIM_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
55 typedef struct
56 {
57  uint16_t TIM_Prescaler;
60  uint16_t TIM_CounterMode;
63  uint32_t TIM_Period;
67  uint16_t TIM_ClockDivision;
70  uint8_t TIM_RepetitionCounter;
78 } TIM_TimeBaseInitTypeDef;
79 
84 typedef struct
85 {
86  uint16_t TIM_OCMode;
89  uint16_t TIM_OutputState;
92  uint16_t TIM_OutputNState;
96  uint32_t TIM_Pulse;
99  uint16_t TIM_OCPolarity;
102  uint16_t TIM_OCNPolarity;
106  uint16_t TIM_OCIdleState;
110  uint16_t TIM_OCNIdleState;
113 } TIM_OCInitTypeDef;
114 
119 typedef struct
120 {
121 
122  uint16_t TIM_Channel;
125  uint16_t TIM_ICPolarity;
128  uint16_t TIM_ICSelection;
131  uint16_t TIM_ICPrescaler;
134  uint16_t TIM_ICFilter;
136 } TIM_ICInitTypeDef;
137 
143 typedef struct
144 {
145 
146  uint16_t TIM_OSSRState;
149  uint16_t TIM_OSSIState;
152  uint16_t TIM_LOCKLevel;
155  uint16_t TIM_DeadTime;
159  uint16_t TIM_Break;
162  uint16_t TIM_BreakPolarity;
165  uint16_t TIM_AutomaticOutput;
167 } TIM_BDTRInitTypeDef;
168 
169 /* Exported constants --------------------------------------------------------*/
170 
175 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
176  ((PERIPH) == TIM2) || \
177  ((PERIPH) == TIM3) || \
178  ((PERIPH) == TIM4) || \
179  ((PERIPH) == TIM5) || \
180  ((PERIPH) == TIM6) || \
181  ((PERIPH) == TIM7) || \
182  ((PERIPH) == TIM8) || \
183  ((PERIPH) == TIM9) || \
184  ((PERIPH) == TIM10) || \
185  ((PERIPH) == TIM11) || \
186  ((PERIPH) == TIM12) || \
187  (((PERIPH) == TIM13) || \
188  ((PERIPH) == TIM14)))
189 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */
190 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
191  ((PERIPH) == TIM2) || \
192  ((PERIPH) == TIM3) || \
193  ((PERIPH) == TIM4) || \
194  ((PERIPH) == TIM5) || \
195  ((PERIPH) == TIM8) || \
196  ((PERIPH) == TIM9) || \
197  ((PERIPH) == TIM10) || \
198  ((PERIPH) == TIM11) || \
199  ((PERIPH) == TIM12) || \
200  ((PERIPH) == TIM13) || \
201  ((PERIPH) == TIM14))
202 
203 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
204 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
205  ((PERIPH) == TIM2) || \
206  ((PERIPH) == TIM3) || \
207  ((PERIPH) == TIM4) || \
208  ((PERIPH) == TIM5) || \
209  ((PERIPH) == TIM8) || \
210  ((PERIPH) == TIM9) || \
211  ((PERIPH) == TIM12))
212 /* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
213 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
214  ((PERIPH) == TIM2) || \
215  ((PERIPH) == TIM3) || \
216  ((PERIPH) == TIM4) || \
217  ((PERIPH) == TIM5) || \
218  ((PERIPH) == TIM8))
219 /* LIST4: TIM1 and TIM8 */
220 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
221  ((PERIPH) == TIM8))
222 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
223 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
224  ((PERIPH) == TIM2) || \
225  ((PERIPH) == TIM3) || \
226  ((PERIPH) == TIM4) || \
227  ((PERIPH) == TIM5) || \
228  ((PERIPH) == TIM6) || \
229  ((PERIPH) == TIM7) || \
230  ((PERIPH) == TIM8))
231 /* LIST6: TIM2, TIM5 and TIM11 */
232 #define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
233  ((TIMx) == TIM5) || \
234  ((TIMx) == TIM11))
235 
240 #define TIM_OCMode_Timing ((uint16_t)0x0000)
241 #define TIM_OCMode_Active ((uint16_t)0x0010)
242 #define TIM_OCMode_Inactive ((uint16_t)0x0020)
243 #define TIM_OCMode_Toggle ((uint16_t)0x0030)
244 #define TIM_OCMode_PWM1 ((uint16_t)0x0060)
245 #define TIM_OCMode_PWM2 ((uint16_t)0x0070)
246 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
247  ((MODE) == TIM_OCMode_Active) || \
248  ((MODE) == TIM_OCMode_Inactive) || \
249  ((MODE) == TIM_OCMode_Toggle)|| \
250  ((MODE) == TIM_OCMode_PWM1) || \
251  ((MODE) == TIM_OCMode_PWM2))
252 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
253  ((MODE) == TIM_OCMode_Active) || \
254  ((MODE) == TIM_OCMode_Inactive) || \
255  ((MODE) == TIM_OCMode_Toggle)|| \
256  ((MODE) == TIM_OCMode_PWM1) || \
257  ((MODE) == TIM_OCMode_PWM2) || \
258  ((MODE) == TIM_ForcedAction_Active) || \
259  ((MODE) == TIM_ForcedAction_InActive))
260 
268 #define TIM_OPMode_Single ((uint16_t)0x0008)
269 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
270 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
271  ((MODE) == TIM_OPMode_Repetitive))
272 
280 #define TIM_Channel_1 ((uint16_t)0x0000)
281 #define TIM_Channel_2 ((uint16_t)0x0004)
282 #define TIM_Channel_3 ((uint16_t)0x0008)
283 #define TIM_Channel_4 ((uint16_t)0x000C)
284 
285 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
286  ((CHANNEL) == TIM_Channel_2) || \
287  ((CHANNEL) == TIM_Channel_3) || \
288  ((CHANNEL) == TIM_Channel_4))
289 
290 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
291  ((CHANNEL) == TIM_Channel_2))
292 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
293  ((CHANNEL) == TIM_Channel_2) || \
294  ((CHANNEL) == TIM_Channel_3))
295 
303 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
304 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
305 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
306 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
307  ((DIV) == TIM_CKD_DIV2) || \
308  ((DIV) == TIM_CKD_DIV4))
309 
317 #define TIM_CounterMode_Up ((uint16_t)0x0000)
318 #define TIM_CounterMode_Down ((uint16_t)0x0010)
319 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
320 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
321 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
322 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
323  ((MODE) == TIM_CounterMode_Down) || \
324  ((MODE) == TIM_CounterMode_CenterAligned1) || \
325  ((MODE) == TIM_CounterMode_CenterAligned2) || \
326  ((MODE) == TIM_CounterMode_CenterAligned3))
327 
335 #define TIM_OCPolarity_High ((uint16_t)0x0000)
336 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
337 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
338  ((POLARITY) == TIM_OCPolarity_Low))
339 
347 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
348 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
349 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
350  ((POLARITY) == TIM_OCNPolarity_Low))
351 
359 #define TIM_OutputState_Disable ((uint16_t)0x0000)
360 #define TIM_OutputState_Enable ((uint16_t)0x0001)
361 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
362  ((STATE) == TIM_OutputState_Enable))
363 
371 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
372 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
373 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
374  ((STATE) == TIM_OutputNState_Enable))
375 
383 #define TIM_CCx_Enable ((uint16_t)0x0001)
384 #define TIM_CCx_Disable ((uint16_t)0x0000)
385 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
386  ((CCX) == TIM_CCx_Disable))
387 
395 #define TIM_CCxN_Enable ((uint16_t)0x0004)
396 #define TIM_CCxN_Disable ((uint16_t)0x0000)
397 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
398  ((CCXN) == TIM_CCxN_Disable))
399 
407 #define TIM_Break_Enable ((uint16_t)0x1000)
408 #define TIM_Break_Disable ((uint16_t)0x0000)
409 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
410  ((STATE) == TIM_Break_Disable))
411 
419 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
420 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
421 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
422  ((POLARITY) == TIM_BreakPolarity_High))
423 
431 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
432 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
433 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
434  ((STATE) == TIM_AutomaticOutput_Disable))
435 
443 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
444 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
445 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
446 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
447 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
448  ((LEVEL) == TIM_LOCKLevel_1) || \
449  ((LEVEL) == TIM_LOCKLevel_2) || \
450  ((LEVEL) == TIM_LOCKLevel_3))
451 
459 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
460 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
461 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
462  ((STATE) == TIM_OSSIState_Disable))
463 
471 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
472 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
473 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
474  ((STATE) == TIM_OSSRState_Disable))
475 
483 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
484 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
485 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
486  ((STATE) == TIM_OCIdleState_Reset))
487 
495 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
496 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
497 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
498  ((STATE) == TIM_OCNIdleState_Reset))
499 
507 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
508 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
509 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
510 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
511  ((POLARITY) == TIM_ICPolarity_Falling)|| \
512  ((POLARITY) == TIM_ICPolarity_BothEdge))
513 
521 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001)
523 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
525 #define TIM_ICSelection_TRC ((uint16_t)0x0003)
526 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
527  ((SELECTION) == TIM_ICSelection_IndirectTI) || \
528  ((SELECTION) == TIM_ICSelection_TRC))
529 
537 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000)
538 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004)
539 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008)
540 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C)
541 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
542  ((PRESCALER) == TIM_ICPSC_DIV2) || \
543  ((PRESCALER) == TIM_ICPSC_DIV4) || \
544  ((PRESCALER) == TIM_ICPSC_DIV8))
545 
553 #define TIM_IT_Update ((uint16_t)0x0001)
554 #define TIM_IT_CC1 ((uint16_t)0x0002)
555 #define TIM_IT_CC2 ((uint16_t)0x0004)
556 #define TIM_IT_CC3 ((uint16_t)0x0008)
557 #define TIM_IT_CC4 ((uint16_t)0x0010)
558 #define TIM_IT_COM ((uint16_t)0x0020)
559 #define TIM_IT_Trigger ((uint16_t)0x0040)
560 #define TIM_IT_Break ((uint16_t)0x0080)
561 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
562 
563 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
564  ((IT) == TIM_IT_CC1) || \
565  ((IT) == TIM_IT_CC2) || \
566  ((IT) == TIM_IT_CC3) || \
567  ((IT) == TIM_IT_CC4) || \
568  ((IT) == TIM_IT_COM) || \
569  ((IT) == TIM_IT_Trigger) || \
570  ((IT) == TIM_IT_Break))
571 
579 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
580 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
581 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
582 #define TIM_DMABase_DIER ((uint16_t)0x0003)
583 #define TIM_DMABase_SR ((uint16_t)0x0004)
584 #define TIM_DMABase_EGR ((uint16_t)0x0005)
585 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
586 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
587 #define TIM_DMABase_CCER ((uint16_t)0x0008)
588 #define TIM_DMABase_CNT ((uint16_t)0x0009)
589 #define TIM_DMABase_PSC ((uint16_t)0x000A)
590 #define TIM_DMABase_ARR ((uint16_t)0x000B)
591 #define TIM_DMABase_RCR ((uint16_t)0x000C)
592 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
593 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
594 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
595 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
596 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
597 #define TIM_DMABase_DCR ((uint16_t)0x0012)
598 #define TIM_DMABase_OR ((uint16_t)0x0013)
599 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
600  ((BASE) == TIM_DMABase_CR2) || \
601  ((BASE) == TIM_DMABase_SMCR) || \
602  ((BASE) == TIM_DMABase_DIER) || \
603  ((BASE) == TIM_DMABase_SR) || \
604  ((BASE) == TIM_DMABase_EGR) || \
605  ((BASE) == TIM_DMABase_CCMR1) || \
606  ((BASE) == TIM_DMABase_CCMR2) || \
607  ((BASE) == TIM_DMABase_CCER) || \
608  ((BASE) == TIM_DMABase_CNT) || \
609  ((BASE) == TIM_DMABase_PSC) || \
610  ((BASE) == TIM_DMABase_ARR) || \
611  ((BASE) == TIM_DMABase_RCR) || \
612  ((BASE) == TIM_DMABase_CCR1) || \
613  ((BASE) == TIM_DMABase_CCR2) || \
614  ((BASE) == TIM_DMABase_CCR3) || \
615  ((BASE) == TIM_DMABase_CCR4) || \
616  ((BASE) == TIM_DMABase_BDTR) || \
617  ((BASE) == TIM_DMABase_DCR) || \
618  ((BASE) == TIM_DMABase_OR))
619 
627 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
628 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
629 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
630 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
631 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
632 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
633 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
634 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
635 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
636 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
637 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
638 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
639 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
640 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
641 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
642 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
643 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
644 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
645 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
646  ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
647  ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
648  ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
649  ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
650  ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
651  ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
652  ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
653  ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
654  ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
655  ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
656  ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
657  ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
658  ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
659  ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
660  ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
661  ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
662  ((LENGTH) == TIM_DMABurstLength_18Transfers))
663 
671 #define TIM_DMA_Update ((uint16_t)0x0100)
672 #define TIM_DMA_CC1 ((uint16_t)0x0200)
673 #define TIM_DMA_CC2 ((uint16_t)0x0400)
674 #define TIM_DMA_CC3 ((uint16_t)0x0800)
675 #define TIM_DMA_CC4 ((uint16_t)0x1000)
676 #define TIM_DMA_COM ((uint16_t)0x2000)
677 #define TIM_DMA_Trigger ((uint16_t)0x4000)
678 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
679 
688 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
689 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
690 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
691 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
692 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
693  ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
694  ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
695  ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
696 
704 #define TIM_TS_ITR0 ((uint16_t)0x0000)
705 #define TIM_TS_ITR1 ((uint16_t)0x0010)
706 #define TIM_TS_ITR2 ((uint16_t)0x0020)
707 #define TIM_TS_ITR3 ((uint16_t)0x0030)
708 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
709 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
710 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
711 #define TIM_TS_ETRF ((uint16_t)0x0070)
712 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
713  ((SELECTION) == TIM_TS_ITR1) || \
714  ((SELECTION) == TIM_TS_ITR2) || \
715  ((SELECTION) == TIM_TS_ITR3) || \
716  ((SELECTION) == TIM_TS_TI1F_ED) || \
717  ((SELECTION) == TIM_TS_TI1FP1) || \
718  ((SELECTION) == TIM_TS_TI2FP2) || \
719  ((SELECTION) == TIM_TS_ETRF))
720 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
721  ((SELECTION) == TIM_TS_ITR1) || \
722  ((SELECTION) == TIM_TS_ITR2) || \
723  ((SELECTION) == TIM_TS_ITR3))
724 
732 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
733 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
734 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
735 
743 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
744 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
745 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
746  ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
747 
755 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
756 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
757 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
758  ((RELOAD) == TIM_PSCReloadMode_Immediate))
759 
767 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
768 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
769 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
770  ((ACTION) == TIM_ForcedAction_InActive))
771 
779 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
780 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
781 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
782 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
783  ((MODE) == TIM_EncoderMode_TI2) || \
784  ((MODE) == TIM_EncoderMode_TI12))
785 
794 #define TIM_EventSource_Update ((uint16_t)0x0001)
795 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
796 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
797 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
798 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
799 #define TIM_EventSource_COM ((uint16_t)0x0020)
800 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
801 #define TIM_EventSource_Break ((uint16_t)0x0080)
802 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
803 
812 #define TIM_UpdateSource_Global ((uint16_t)0x0000)
815 #define TIM_UpdateSource_Regular ((uint16_t)0x0001)
816 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
817  ((SOURCE) == TIM_UpdateSource_Regular))
818 
826 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
827 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
828 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
829  ((STATE) == TIM_OCPreload_Disable))
830 
838 #define TIM_OCFast_Enable ((uint16_t)0x0004)
839 #define TIM_OCFast_Disable ((uint16_t)0x0000)
840 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
841  ((STATE) == TIM_OCFast_Disable))
842 
851 #define TIM_OCClear_Enable ((uint16_t)0x0080)
852 #define TIM_OCClear_Disable ((uint16_t)0x0000)
853 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
854  ((STATE) == TIM_OCClear_Disable))
855 
863 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
864 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
865 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
866 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
867 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
868 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
869 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
870 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
871 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
872  ((SOURCE) == TIM_TRGOSource_Enable) || \
873  ((SOURCE) == TIM_TRGOSource_Update) || \
874  ((SOURCE) == TIM_TRGOSource_OC1) || \
875  ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
876  ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
877  ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
878  ((SOURCE) == TIM_TRGOSource_OC4Ref))
879 
887 #define TIM_SlaveMode_Reset ((uint16_t)0x0004)
888 #define TIM_SlaveMode_Gated ((uint16_t)0x0005)
889 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
890 #define TIM_SlaveMode_External1 ((uint16_t)0x0007)
891 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
892  ((MODE) == TIM_SlaveMode_Gated) || \
893  ((MODE) == TIM_SlaveMode_Trigger) || \
894  ((MODE) == TIM_SlaveMode_External1))
895 
903 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
904 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
905 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
906  ((STATE) == TIM_MasterSlaveMode_Disable))
907 
914 #define TIM2_TIM8_TRGO ((uint16_t)0x0000)
915 #define TIM2_ETH_PTP ((uint16_t)0x0400)
916 #define TIM2_USBFS_SOF ((uint16_t)0x0800)
917 #define TIM2_USBHS_SOF ((uint16_t)0x0C00)
918 
919 #define TIM5_GPIO ((uint16_t)0x0000)
920 #define TIM5_LSI ((uint16_t)0x0040)
921 #define TIM5_LSE ((uint16_t)0x0080)
922 #define TIM5_RTC ((uint16_t)0x00C0)
923 
924 #define TIM11_GPIO ((uint16_t)0x0000)
925 #define TIM11_HSE ((uint16_t)0x0002)
926 
927 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
928  ((TIM_REMAP) == TIM2_ETH_PTP)||\
929  ((TIM_REMAP) == TIM2_USBFS_SOF)||\
930  ((TIM_REMAP) == TIM2_USBHS_SOF)||\
931  ((TIM_REMAP) == TIM5_GPIO)||\
932  ((TIM_REMAP) == TIM5_LSI)||\
933  ((TIM_REMAP) == TIM5_LSE)||\
934  ((TIM_REMAP) == TIM5_RTC)||\
935  ((TIM_REMAP) == TIM11_GPIO)||\
936  ((TIM_REMAP) == TIM11_HSE))
937 
945 #define TIM_FLAG_Update ((uint16_t)0x0001)
946 #define TIM_FLAG_CC1 ((uint16_t)0x0002)
947 #define TIM_FLAG_CC2 ((uint16_t)0x0004)
948 #define TIM_FLAG_CC3 ((uint16_t)0x0008)
949 #define TIM_FLAG_CC4 ((uint16_t)0x0010)
950 #define TIM_FLAG_COM ((uint16_t)0x0020)
951 #define TIM_FLAG_Trigger ((uint16_t)0x0040)
952 #define TIM_FLAG_Break ((uint16_t)0x0080)
953 #define TIM_FLAG_CC1OF ((uint16_t)0x0200)
954 #define TIM_FLAG_CC2OF ((uint16_t)0x0400)
955 #define TIM_FLAG_CC3OF ((uint16_t)0x0800)
956 #define TIM_FLAG_CC4OF ((uint16_t)0x1000)
957 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
958  ((FLAG) == TIM_FLAG_CC1) || \
959  ((FLAG) == TIM_FLAG_CC2) || \
960  ((FLAG) == TIM_FLAG_CC3) || \
961  ((FLAG) == TIM_FLAG_CC4) || \
962  ((FLAG) == TIM_FLAG_COM) || \
963  ((FLAG) == TIM_FLAG_Trigger) || \
964  ((FLAG) == TIM_FLAG_Break) || \
965  ((FLAG) == TIM_FLAG_CC1OF) || \
966  ((FLAG) == TIM_FLAG_CC2OF) || \
967  ((FLAG) == TIM_FLAG_CC3OF) || \
968  ((FLAG) == TIM_FLAG_CC4OF))
969 
978 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
979 
987 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
988 
996 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
997 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
998 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
999 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
1000 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
1001 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
1002 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
1003 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
1004 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
1005 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
1006 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
1007 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
1008 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
1009 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
1010 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
1011 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
1012 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
1013 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
1014 
1022 /* Exported macro ------------------------------------------------------------*/
1023 /* Exported functions --------------------------------------------------------*/
1024 
1025 /* TimeBase management ********************************************************/
1026 void TIM_DeInit(TIM_TypeDef* TIMx);
1027 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1028 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1029 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
1030 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
1031 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
1032 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
1033 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
1034 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
1035 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1036 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
1037 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1038 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
1039 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
1040 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1041 
1042 /* Output Compare management **************************************************/
1043 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1044 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1045 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1046 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1047 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
1048 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
1049 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
1050 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
1051 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
1052 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
1053 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1054 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1055 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1056 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1057 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1058 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1059 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1060 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1061 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1062 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1063 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1064 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1065 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1066 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1067 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1068 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1069 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1070 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1071 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1072 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1073 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1074 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1075 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1076 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
1077 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
1078 
1079 /* Input Capture management ***************************************************/
1080 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1081 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
1082 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1083 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
1084 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
1085 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
1086 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
1087 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1088 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1089 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1090 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1091 
1092 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/
1093 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
1094 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
1095 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
1096 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
1097 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
1098 
1099 /* Interrupts, DMA and flags management ***************************************/
1100 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
1101 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
1102 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1103 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1104 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1105 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1106 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
1107 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
1108 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
1109 
1110 /* Clocks management **********************************************************/
1111 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
1112 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1113 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
1114  uint16_t TIM_ICPolarity, uint16_t ICFilter);
1115 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1116  uint16_t ExtTRGFilter);
1117 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
1118  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
1119 
1120 /* Synchronization management *************************************************/
1121 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1122 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
1123 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
1124 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
1125 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1126  uint16_t ExtTRGFilter);
1127 
1128 /* Specific interface management **********************************************/
1129 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
1130  uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
1131 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
1132 
1133 /* Specific remapping management **********************************************/
1134 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
1135 
1136 #ifdef __cplusplus
1137 }
1138 #endif
1139 
1140 #endif /*__STM32F4xx_TIM_H */
1141 
1150 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
TIM_BDTRInitTypeDef::TIM_Break
uint16_t TIM_Break
Definition: stm32f4xx_tim.h:159
TIM_SelectHallSensor
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
Definition: stm32f4xx_tim.c:3122
TIM_CtrlPWMOutputs
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
Definition: stm32f4xx_tim.c:2265
TIM_SelectCCDMA
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
Definition: stm32f4xx_tim.c:2644
TIM_BDTRInitTypeDef::TIM_BreakPolarity
uint16_t TIM_BreakPolarity
Definition: stm32f4xx_tim.h:162
TIM_SetCompare2
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
Definition: stm32f4xx_tim.c:1076
TIM_Cmd
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
Definition: stm32f4xx_tim.c:592
TIM_BDTRInitTypeDef::TIM_DeadTime
uint16_t TIM_DeadTime
Definition: stm32f4xx_tim.h:155
TIM_ClearOC4Ref
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
Definition: stm32f4xx_tim.c:1564
TIM_OC3FastConfig
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
Definition: stm32f4xx_tim.c:1416
TIM_TimeBaseInitTypeDef::TIM_Prescaler
uint16_t TIM_Prescaler
Definition: stm32f4xx_tim.h:57
TIM_GetPrescaler
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
Definition: stm32f4xx_tim.c:452
TIM_SetIC2Prescaler
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
Definition: stm32f4xx_tim.c:2120
TIM_SetIC3Prescaler
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
Definition: stm32f4xx_tim.c:2144
TIM_OC3PolarityConfig
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
Definition: stm32f4xx_tim.c:1701
TIM_GetCapture2
uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
Definition: stm32f4xx_tim.c:2047
TIM_ICInitTypeDef::TIM_ICPolarity
uint16_t TIM_ICPolarity
Definition: stm32f4xx_tim.h:125
TIM_BDTRInitTypeDef::TIM_OSSRState
uint16_t TIM_OSSRState
Definition: stm32f4xx_tim.h:146
TIM_OCStructInit
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
Definition: stm32f4xx_tim.c:978
TIM_OC3Init
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:835
TIM_ClearOC1Ref
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
Definition: stm32f4xx_tim.c:1476
TIM_SelectOnePulseMode
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
Definition: stm32f4xx_tim.c:549
TIM_TimeBaseInitTypeDef::TIM_Period
uint32_t TIM_Period
Definition: stm32f4xx_tim.h:63
TIM_OC3PreloadConfig
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
Definition: stm32f4xx_tim.c:1297
TIM_OC2NPolarityConfig
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
Definition: stm32f4xx_tim.c:1674
TIM_ITRxExternalClockConfig
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
Definition: stm32f4xx_tim.c:2704
TIM_SelectCOM
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
Definition: stm32f4xx_tim.c:2290
TIM_OC4FastConfig
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
Definition: stm32f4xx_tim.c:1446
TIM_ForcedOC3Config
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1181
TIM_ETRConfig
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
Definition: stm32f4xx_tim.c:3012
TIM_ARRPreloadConfig
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
Definition: stm32f4xx_tim.c:522
TIM_GetCapture3
uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
Definition: stm32f4xx_tim.c:2061
TIM_CCxCmd
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
Definition: stm32f4xx_tim.c:1786
TIM_ETRClockMode2Config
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
Definition: stm32f4xx_tim.c:2821
TIM_ForcedOC2Config
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1153
TIM_PrescalerConfig
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
Definition: stm32f4xx_tim.c:360
TIM_OCInitTypeDef::TIM_OCNPolarity
uint16_t TIM_OCNPolarity
Definition: stm32f4xx_tim.h:102
TIM_OCInitTypeDef::TIM_OCNIdleState
uint16_t TIM_OCNIdleState
Definition: stm32f4xx_tim.h:110
TIM_OC1Init
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:673
TIM_TimeBaseInitTypeDef::TIM_ClockDivision
uint16_t TIM_ClockDivision
Definition: stm32f4xx_tim.h:67
TIM_OC2Init
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:754
TIM_ICStructInit
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
Definition: stm32f4xx_tim.c:1956
TIM_DMACmd
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
Definition: stm32f4xx_tim.c:2618
TIM_SetCounter
void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
Definition: stm32f4xx_tim.c:409
TIM_ICInitTypeDef::TIM_ICPrescaler
uint16_t TIM_ICPrescaler
Definition: stm32f4xx_tim.h:131
TIM_SetCompare3
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
Definition: stm32f4xx_tim.c:1091
TIM_ETRClockMode1Config
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
Definition: stm32f4xx_tim.c:2774
TIM_UpdateDisableConfig
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
Definition: stm32f4xx_tim.c:468
TIM_ForcedOC1Config
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1124
TIM_ICInit
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
Definition: stm32f4xx_tim.c:1900
TIM_BDTRInitTypeDef::TIM_OSSIState
uint16_t TIM_OSSIState
Definition: stm32f4xx_tim.h:149
TIM_ClearFlag
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
Definition: stm32f4xx_tim.c:2485
TIM_SetIC4Prescaler
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
Definition: stm32f4xx_tim.c:2168
TIM_OCInitTypeDef::TIM_Pulse
uint32_t TIM_Pulse
Definition: stm32f4xx_tim.h:96
TIM_ClearOC3Ref
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
Definition: stm32f4xx_tim.c:1535
TIM_OCInitTypeDef
TIM Output Compare Init structure definition.
Definition: stm32f4xx_tim.h:84
TIM_BDTRConfig
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output ena...
Definition: stm32f4xx_tim.c:2221
TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition.
Definition: stm32f4xx_tim.h:55
TIM_CCPreloadControl
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
Definition: stm32f4xx_tim.c:2315
TIM_SelectMasterSlaveMode
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
Definition: stm32f4xx_tim.c:2982
TIM_ClearOC2Ref
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
Definition: stm32f4xx_tim.c:1506
TIM_SetCompare1
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
Definition: stm32f4xx_tim.c:1060
TIM_GetFlagStatus
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
Definition: stm32f4xx_tim.c:2443
TIM_EncoderInterfaceConfig
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
Definition: stm32f4xx_tim.c:3070
TIM_SetIC1Prescaler
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
Definition: stm32f4xx_tim.c:2095
TIM_SetClockDivision
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
Definition: stm32f4xx_tim.c:572
TIM_OC1PreloadConfig
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
Definition: stm32f4xx_tim.c:1238
TIM_ICInitTypeDef::TIM_Channel
uint16_t TIM_Channel
Definition: stm32f4xx_tim.h:122
TIM_SelectOCxM
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
Definition: stm32f4xx_tim.c:1014
TIM_ClearITPendingBit
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
Definition: stm32f4xx_tim.c:2554
TIM_OC1NPolarityConfig
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
Definition: stm32f4xx_tim.c:1620
TIM_GetCapture1
uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
Definition: stm32f4xx_tim.c:2032
TIM_OCInitTypeDef::TIM_OCMode
uint16_t TIM_OCMode
Definition: stm32f4xx_tim.h:86
TIM_GetCounter
uint32_t TIM_GetCounter(TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
Definition: stm32f4xx_tim.c:438
TIM_GenerateEvent
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
Definition: stm32f4xx_tim.c:2410
TIM_BDTRInitTypeDef::TIM_LOCKLevel
uint16_t TIM_LOCKLevel
Definition: stm32f4xx_tim.h:152
TIM_ICInitTypeDef::TIM_ICSelection
uint16_t TIM_ICSelection
Definition: stm32f4xx_tim.h:128
TIM_UpdateRequestConfig
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.
Definition: stm32f4xx_tim.c:497
TIM_OCInitTypeDef::TIM_OCPolarity
uint16_t TIM_OCPolarity
Definition: stm32f4xx_tim.h:99
TIM_OC1PolarityConfig
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
Definition: stm32f4xx_tim.c:1593
TIM_OC4PolarityConfig
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
Definition: stm32f4xx_tim.c:1755
TIM_TIxExternalClockConfig
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
Definition: stm32f4xx_tim.c:2734
TIM_CounterModeConfig
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
Definition: stm32f4xx_tim.c:383
TIM_TimeBaseInit
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeB...
Definition: stm32f4xx_tim.c:288
TIM_CCxNCmd
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
Definition: stm32f4xx_tim.c:1816
TIM_GetITStatus
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
Definition: stm32f4xx_tim.c:2513
TIM_ForcedOC4Config
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1210
TIM_SelectInputTrigger
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
Definition: stm32f4xx_tim.c:2892
TIM_ICInitTypeDef
TIM Input Capture Init structure definition.
Definition: stm32f4xx_tim.h:119
TIM_SelectSlaveMode
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
Definition: stm32f4xx_tim.c:2959
TIM_BDTRStructInit
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
Definition: stm32f4xx_tim.c:2246
TIM_OC2PolarityConfig
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
Definition: stm32f4xx_tim.c:1647
TIM_SetAutoreload
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
Definition: stm32f4xx_tim.c:424
TIM_DeInit
void TIM_DeInit(TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
Definition: stm32f4xx_tim.c:200
TIM_OCInitTypeDef::TIM_OutputState
uint16_t TIM_OutputState
Definition: stm32f4xx_tim.h:89
TIM_OC1FastConfig
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
Definition: stm32f4xx_tim.c:1355
TIM_GetCapture4
uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
Definition: stm32f4xx_tim.c:2075
TIM_OCInitTypeDef::TIM_OCIdleState
uint16_t TIM_OCIdleState
Definition: stm32f4xx_tim.h:106
TIM_DMAConfig
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
Definition: stm32f4xx_tim.c:2591
TIM_BDTRInitTypeDef::TIM_AutomaticOutput
uint16_t TIM_AutomaticOutput
Definition: stm32f4xx_tim.h:165
TIM_TimeBaseStructInit
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
Definition: stm32f4xx_tim.c:340
TIM_ITConfig
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
Definition: stm32f4xx_tim.c:2372
TIM_SelectOutputTrigger
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
Definition: stm32f4xx_tim.c:2935
TIM_TimeBaseInitTypeDef::TIM_CounterMode
uint16_t TIM_CounterMode
Definition: stm32f4xx_tim.h:60
TIM_InternalClockConfig
void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
Definition: stm32f4xx_tim.c:2683
TIM_OC2PreloadConfig
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
Definition: stm32f4xx_tim.c:1268
TIM_RemapConfig
void TIM_RemapConfig(TIM_TypeDef *TIMx, uint16_t TIM_Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
Definition: stm32f4xx_tim.c:3173
TIM_OC2FastConfig
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
Definition: stm32f4xx_tim.c:1386
TIM_OCInitTypeDef::TIM_OutputNState
uint16_t TIM_OutputNState
Definition: stm32f4xx_tim.h:92
TIM_ICInitTypeDef::TIM_ICFilter
uint16_t TIM_ICFilter
Definition: stm32f4xx_tim.h:134
TIM_OC4PreloadConfig
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
Definition: stm32f4xx_tim.c:1326
TIM_OC3NPolarityConfig
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
Definition: stm32f4xx_tim.c:1728
TIM_BDTRInitTypeDef
BDTR structure definition.
Definition: stm32f4xx_tim.h:143
TIM_SetCompare4
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
Definition: stm32f4xx_tim.c:1106
TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter
uint8_t TIM_RepetitionCounter
Definition: stm32f4xx_tim.h:70
TIM_PWMIConfig
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measur...
Definition: stm32f4xx_tim.c:1975
TIM_OC4Init
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:915