CARME-M4 BSP  V1.5
stm32f4xx_pwr.c
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1 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_pwr.h"
39 #include "stm32f4xx_rcc.h"
40 
50 /* Private typedef -----------------------------------------------------------*/
51 /* Private define ------------------------------------------------------------*/
52 /* --------- PWR registers bit address in the alias region ---------- */
53 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
54 
55 /* --- CR Register ---*/
56 
57 /* Alias word address of DBP bit */
58 #define CR_OFFSET (PWR_OFFSET + 0x00)
59 #define DBP_BitNumber 0x08
60 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
61 
62 /* Alias word address of PVDE bit */
63 #define PVDE_BitNumber 0x04
64 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
65 
66 /* Alias word address of FPDS bit */
67 #define FPDS_BitNumber 0x09
68 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
69 
70 /* Alias word address of PMODE bit */
71 #define PMODE_BitNumber 0x0E
72 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
73 
74 /* Alias word address of ODEN bit */
75 #define ODEN_BitNumber 0x10
76 #define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
77 
78 /* Alias word address of ODSWEN bit */
79 #define ODSWEN_BitNumber 0x11
80 #define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
81 
82 /* --- CSR Register ---*/
83 
84 /* Alias word address of EWUP bit */
85 #define CSR_OFFSET (PWR_OFFSET + 0x04)
86 #define EWUP_BitNumber 0x08
87 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
88 
89 /* Alias word address of BRE bit */
90 #define BRE_BitNumber 0x09
91 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
92 
93 /* ------------------ PWR registers bit mask ------------------------ */
94 
95 /* CR register bit mask */
96 #define CR_DS_MASK ((uint32_t)0xFFFFF3FC)
97 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
98 #define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
99 
100 /* Private macro -------------------------------------------------------------*/
101 /* Private variables ---------------------------------------------------------*/
102 /* Private function prototypes -----------------------------------------------*/
103 /* Private functions ---------------------------------------------------------*/
104 
134 void PWR_DeInit(void)
135 {
136  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
137  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
138 }
139 
149 void PWR_BackupAccessCmd(FunctionalState NewState)
150 {
151  /* Check the parameters */
152  assert_param(IS_FUNCTIONAL_STATE(NewState));
153 
154  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
155 }
156 
197 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
198 {
199  uint32_t tmpreg = 0;
200 
201  /* Check the parameters */
202  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
203 
204  tmpreg = PWR->CR;
205 
206  /* Clear PLS[7:5] bits */
207  tmpreg &= CR_PLS_MASK;
208 
209  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
210  tmpreg |= PWR_PVDLevel;
211 
212  /* Store the new value */
213  PWR->CR = tmpreg;
214 }
215 
222 void PWR_PVDCmd(FunctionalState NewState)
223 {
224  /* Check the parameters */
225  assert_param(IS_FUNCTIONAL_STATE(NewState));
226 
227  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
228 }
229 
256 void PWR_WakeUpPinCmd(FunctionalState NewState)
257 {
258  /* Check the parameters */
259  assert_param(IS_FUNCTIONAL_STATE(NewState));
260 
261  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
262 }
263 
353 void PWR_BackupRegulatorCmd(FunctionalState NewState)
354 {
355  /* Check the parameters */
356  assert_param(IS_FUNCTIONAL_STATE(NewState));
357 
358  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
359 }
360 
375 void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
376 {
377  uint32_t tmpreg = 0;
378 
379  /* Check the parameters */
380  assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
381 
382  tmpreg = PWR->CR;
383 
384  /* Clear VOS[15:14] bits */
385  tmpreg &= CR_VOS_MASK;
386 
387  /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
388  tmpreg |= PWR_Regulator_Voltage;
389 
390  /* Store the new value */
391  PWR->CR = tmpreg;
392 }
393 
410 void PWR_OverDriveCmd(FunctionalState NewState)
411 {
412  /* Check the parameters */
413  assert_param(IS_FUNCTIONAL_STATE(NewState));
414 
415  /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */
416  *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState;
417 }
418 
428 void PWR_OverDriveSWCmd(FunctionalState NewState)
429 {
430  /* Check the parameters */
431  assert_param(IS_FUNCTIONAL_STATE(NewState));
432 
433  /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */
434  *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState;
435 }
436 
455 void PWR_UnderDriveCmd(FunctionalState NewState)
456 {
457  /* Check the parameters */
458  assert_param(IS_FUNCTIONAL_STATE(NewState));
459 
460  if (NewState != DISABLE)
461  {
462  /* Set the UDEN[1:0] bits to enable the Under Drive mode */
463  PWR->CR |= (uint32_t)PWR_CR_UDEN;
464  }
465  else
466  {
467  /* Reset the UDEN[1:0] bits to disable the Under Drive mode */
468  PWR->CR &= (uint32_t)(~PWR_CR_UDEN);
469  }
470 }
471 
499 void PWR_FlashPowerDownCmd(FunctionalState NewState)
500 {
501  /* Check the parameters */
502  assert_param(IS_FUNCTIONAL_STATE(NewState));
503 
504  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
505 }
506 
645 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
646 {
647  uint32_t tmpreg = 0;
648 
649  /* Check the parameters */
650  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
651  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
652 
653  /* Select the regulator state in STOP mode ---------------------------------*/
654  tmpreg = PWR->CR;
655  /* Clear PDDS and LPDS bits */
656  tmpreg &= CR_DS_MASK;
657 
658  /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */
659  tmpreg |= PWR_Regulator;
660 
661  /* Store the new value */
662  PWR->CR = tmpreg;
663 
664  /* Set SLEEPDEEP bit of Cortex System Control Register */
665  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
666 
667  /* Select STOP mode entry --------------------------------------------------*/
668  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
669  {
670  /* Request Wait For Interrupt */
671  __WFI();
672  }
673  else
674  {
675  /* Request Wait For Event */
676  __WFE();
677  }
678  /* Reset SLEEPDEEP bit of Cortex System Control Register */
679  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
680 }
681 
709 void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
710 {
711  uint32_t tmpreg = 0;
712 
713  /* Check the parameters */
714  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator));
715  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
716 
717  /* Select the regulator state in STOP mode ---------------------------------*/
718  tmpreg = PWR->CR;
719  /* Clear PDDS and LPDS bits */
720  tmpreg &= CR_DS_MASK;
721 
722  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
723  tmpreg |= PWR_Regulator;
724 
725  /* Store the new value */
726  PWR->CR = tmpreg;
727 
728  /* Set SLEEPDEEP bit of Cortex System Control Register */
729  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
730 
731  /* Select STOP mode entry --------------------------------------------------*/
732  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
733  {
734  /* Request Wait For Interrupt */
735  __WFI();
736  }
737  else
738  {
739  /* Request Wait For Event */
740  __WFE();
741  }
742  /* Reset SLEEPDEEP bit of Cortex System Control Register */
743  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
744 }
745 
758 {
759  /* Clear Wakeup flag */
760  PWR->CR |= PWR_CR_CWUF;
761 
762  /* Select STANDBY mode */
763  PWR->CR |= PWR_CR_PDDS;
764 
765  /* Set SLEEPDEEP bit of Cortex System Control Register */
766  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
767 
768 /* This option is used to ensure that store operations are completed */
769 #if defined ( __CC_ARM )
770  __force_stores();
771 #endif
772  /* Request Wait For Interrupt */
773  __WFI();
774 }
775 
820 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
821 {
822  FlagStatus bitstatus = RESET;
823 
824  /* Check the parameters */
825  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
826 
827  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
828  {
829  bitstatus = SET;
830  }
831  else
832  {
833  bitstatus = RESET;
834  }
835  /* Return the flag status */
836  return bitstatus;
837 }
838 
848 void PWR_ClearFlag(uint32_t PWR_FLAG)
849 {
850  /* Check the parameters */
851  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
852 
853 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
854  if (PWR_FLAG != PWR_FLAG_UDRDY)
855  {
856  PWR->CR |= PWR_FLAG << 2;
857  }
858  else
859  {
860  PWR->CSR |= PWR_FLAG_UDRDY;
861  }
862 #endif /* STM32F427_437xx || STM32F429_439xx */
863 
864 #if defined (STM32F40_41xxx) || defined (STM32F401xx)
865  PWR->CR |= PWR_FLAG << 2;
866 #endif /* STM32F40_41xxx */
867 }
868 
885 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
This file contains all the functions prototypes for the RCC firmware library.
void PWR_EnterSTANDBYMode(void)
Enters STANDBY mode.
void PWR_FlashPowerDownCmd(FunctionalState NewState)
Enables or disables the Flash Power Down in STOP mode.
void PWR_PVDCmd(FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
This file contains all the functions prototypes for the PWR firmware library.
void PWR_OverDriveSWCmd(FunctionalState NewState)
Enables or disables the Over-Drive switching.
void PWR_BackupAccessCmd(FunctionalState NewState)
Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup ...
void PWR_OverDriveCmd(FunctionalState NewState)
Enables or disables the Over-Drive.
void PWR_UnderDriveCmd(FunctionalState NewState)
Enables or disables the Under-Drive mode.
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
void PWR_ClearFlag(uint32_t PWR_FLAG)
Clears the PWR's pending flags.
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void PWR_BackupRegulatorCmd(FunctionalState NewState)
Enables or disables the Backup Regulator.
void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters in Under-Drive STOP mode.
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void PWR_WakeUpPinCmd(FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
Configures the main internal regulator output voltage.
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
void PWR_DeInit(void)
Deinitializes the PWR peripheral registers to their default reset values.