FLASH Interface configuration functions. More...

Collaboration diagram for FLASH Interface configuration functions:

Functions
void	FLASH_SetLatency (uint32_t FLASH_Latency)
	Sets the code latency value. More...

void	FLASH_PrefetchBufferCmd (FunctionalState NewState)
	Enables or disables the Prefetch Buffer. More...

void	FLASH_InstructionCacheCmd (FunctionalState NewState)
	Enables or disables the Instruction Cache feature. More...

void	FLASH_DataCacheCmd (FunctionalState NewState)
	Enables or disables the Data Cache feature. More...

void	FLASH_InstructionCacheReset (void)
	Resets the Instruction Cache. More...

void	FLASH_DataCacheReset (void)
	Resets the Data Cache. More...

Detailed Description

FLASH Interface configuration functions.

 ===============================================================================
              ##### FLASH Interface configuration functions #####
 ===============================================================================
    [..]
      This group includes the following functions:
      (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
          To correctly read data from FLASH memory, the number of wait states (LATENCY) 
          must be correctly programmed according to the frequency of the CPU clock 
          (HCLK) and the supply voltage of the device.
    [..]      
      For STM32F405xx/07xx and STM32F415xx/17xx devices
 +-------------------------------------------------------------------------------------+     
 | Latency       |                HCLK clock frequency (MHz)                           |
 |               |---------------------------------------------------------------------|     
 |               | voltage range  | voltage range  | voltage range   | voltage range   |
 |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
 |---------------|----------------|----------------|-----------------|-----------------|              
 |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
 |---------------|----------------|----------------|-----------------|-----------------|   
 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  | 
 |---------------|----------------|----------------|-----------------|-----------------|   
 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
 |---------------|----------------|----------------|-----------------|-----------------| 
 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
 |---------------|----------------|----------------|-----------------|-----------------| 
 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
 |---------------|----------------|----------------|-----------------|-----------------| 
 |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| 
 |---------------|----------------|----------------|-----------------|-----------------| 
 |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| 
 |---------------|----------------|----------------|-----------------|-----------------| 
 |7WS(8CPU cycle)|      NA        |      NA        |154 < HCLK <= 168|140 < HCLK <= 160|
 +---------------|----------------|----------------|-----------------|-----------------+ 

    [..]      
      For STM32F42xxx/43xxx devices
 +-------------------------------------------------------------------------------------+     
 | Latency       |                HCLK clock frequency (MHz)                           |
 |               |---------------------------------------------------------------------|     
 |               | voltage range  | voltage range  | voltage range   | voltage range   |
 |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
 |---------------|----------------|----------------|-----------------|-----------------|              
 |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
 |---------------|----------------|----------------|-----------------|-----------------|   
 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  | 
 |---------------|----------------|----------------|-----------------|-----------------|   
 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
 |---------------|----------------|----------------|-----------------|-----------------| 
 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
 |---------------|----------------|----------------|-----------------|-----------------| 
 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
 |---------------|----------------|----------------|-----------------|-----------------| 
 |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| 
 |---------------|----------------|----------------|-----------------|-----------------| 
 |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| 
 |---------------|----------------|----------------|-----------------|-----------------| 
 |7WS(8CPU cycle)|      NA        |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
 |---------------|----------------|----------------|-----------------|-----------------| 
 |8WS(9CPU cycle)|      NA        |      NA        |176 < HCLK <= 180|160 < HCLK <= 168|
 +-------------------------------------------------------------------------------------+
   
    [..]
    For STM32F401x devices
 +-------------------------------------------------------------------------------------+     
 | Latency       |                HCLK clock frequency (MHz)                           |
 |               |---------------------------------------------------------------------|     
 |               | voltage range  | voltage range  | voltage range   | voltage range   |
 |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
 |---------------|----------------|----------------|-----------------|-----------------|              
 |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
 |---------------|----------------|----------------|-----------------|-----------------|   
 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  | 
 |---------------|----------------|----------------|-----------------|-----------------|   
 |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
 |---------------|----------------|----------------|-----------------|-----------------| 
 |3WS(4CPU cycle)|      NA        |72 < HCLK <= 84 |66 < HCLK <= 84  |60 < HCLK <= 80  |
 |---------------|----------------|----------------|-----------------|-----------------| 
 |4WS(5CPU cycle)|      NA        |      NA        |      NA         |80 < HCLK <= 84  | 
 +-------------------------------------------------------------------------------------+ 
 
 [..]
 +-------------------------------------------------------------------------------------------------------------------+
 |               | voltage range  | voltage range  | voltage range   | voltage range   | voltage range 2.7 V - 3.6 V |
 |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   | with External Vpp = 9V      |
 |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| 
 |Max Parallelism|      x32       |               x16                |       x8        |          x64                |              
 |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|   
 |PSIZE[1:0]     |      10        |               01                 |       00        |           11                |
 +-------------------------------------------------------------------------------------------------------------------+  

      -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: 
           (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. 
           (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. 
          [..] 
          On STM32F42xxx/43xxx devices:
           (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
           (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
           (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. 
          [..]  
          On STM32F401x devices:
           (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
           (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
           For more details please refer product DataSheet 
           You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
                 
      (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
      (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
      (+) void FLASH_DataCacheCmd(FunctionalState NewState)
      (+) void FLASH_InstructionCacheReset(void)
      (+) void FLASH_DataCacheReset(void)
      
    [..]   
      The unlock sequence is not needed for these functions.

Function Documentation

void FLASH_DataCacheCmd ( FunctionalState NewState )

Enables or disables the Data Cache feature.

Parameters

NewState new state of the Data Cache. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 306 of file stm32f4xx_flash.c.

void FLASH_DataCacheReset ( void )

Resets the Data Cache.

Note: This function must be used only when the Data Cache is disabled.

Parameters

None

Return values

None

Definition at line 338 of file stm32f4xx_flash.c.

void FLASH_InstructionCacheCmd ( FunctionalState NewState )

Enables or disables the Instruction Cache feature.

Parameters

NewState new state of the Instruction Cache. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 285 of file stm32f4xx_flash.c.

void FLASH_InstructionCacheReset ( void )

Resets the Instruction Cache.

Note: This function must be used only when the Instruction Cache is disabled.

Parameters

None

Return values

None

Definition at line 327 of file stm32f4xx_flash.c.

void FLASH_PrefetchBufferCmd ( FunctionalState NewState )

Enables or disables the Prefetch Buffer.

Parameters

NewState new state of the Prefetch Buffer. This parameter can be: ENABLE or DISABLE.

Return values

None

Definition at line 263 of file stm32f4xx_flash.c.

void FLASH_SetLatency ( uint32_t FLASH_Latency )

Sets the code latency value.

Parameters

FLASH_Latency

specifies the FLASH Latency value. This parameter can be one of the following values:

FLASH_Latency_0: FLASH Zero Latency cycle
FLASH_Latency_1: FLASH One Latency cycle
FLASH_Latency_2: FLASH Two Latency cycles
FLASH_Latency_3: FLASH Three Latency cycles
FLASH_Latency_4: FLASH Four Latency cycles
FLASH_Latency_5: FLASH Five Latency cycles
FLASH_Latency_6: FLASH Six Latency cycles
FLASH_Latency_7: FLASH Seven Latency cycles
FLASH_Latency_8: FLASH Eight Latency cycles
FLASH_Latency_9: FLASH Nine Latency cycles
FLASH_Latency_10: FLASH Teen Latency cycles
FLASH_Latency_11: FLASH Eleven Latency cycles
FLASH_Latency_12: FLASH Twelve Latency cycles
FLASH_Latency_13: FLASH Thirteen Latency cycles
FLASH_Latency_14: FLASH Fourteen Latency cycles
FLASH_Latency_15: FLASH Fifteen Latency cycles

Note: For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx devices this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.; For STM32F42xxx/43xxx devices this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_15.

Return values

None

Definition at line 248 of file stm32f4xx_flash.c.

Functions

Detailed Description

Function Documentation